To increase density in a magnetic random access memory (MRAM) array, it is known to use a memory cell architecture that includes more than one magnetic storage element. For example, U.S. Patent Publication No. 2005/0087785 entitled “Magnetic Random Access Memory Cell” discusses an n-transistor, n-MTJ (magnetic tunnel junction) memory cell providing increased cell density without significantly reducing a lateral size of the MTJ device associated with the memory cell. Conventional multiple-bit memory cell architectures, however, may exhibit a reduced write margin due (at least in part) to the fact that a region of operation during writing may be substantially symmetrical in all four quadrants of a write plane in which the memory cell is written. Consequently, the multiple bits in a given memory cell share the region of operation with one another.
U.S. Pat. No. 7,109,539 entitled “Multiple-Bit Magnetic Random Access Memory Cell Employing Adiabatic Switching” discusses a multiple bit memory cell for use in a magnetic random access memory device. More particularly, the multiple-bit memory cell includes a first adiabatic switching storage element having a first anisotropy axis associated therewith and a second adiabatic switching storage element having a second anisotropy axis associated therewith. The first anisotropy axis and the second anisotropy axis are oriented at a substantially non-zero angle relative to at least one bit line and at least one word line corresponding to the memory cell. The memory cell is configured such that two quadrants of a write plane not used for writing one of the storage elements can be beneficially utilized to write the other storage element so that there is essentially no loss of write margin in the memory cell.